The timing between the rising edges of two pulse signals can be determined by an edge triggered D-type flip flop, with its D input connected to a high logic level. The rising edge of a pulse applied to the clock input of the flip flop sets the flip flop, causing the rising edge of an output signal pulse to be generated, and a pulse applied to the reset input of the flip flop clears the flip flop, causing the falling edge of the output signal pulse to be generated.
However, the shortest time interval of the output pulse using this technique is limited by the reset recovery time of the flip flop, and how narrow the reset pulse can be made. This technique is thus not suitable for high frequency pulse signals, signals having very short differentials in timing between input (set and reset) signals, and input signals having very short pulse widths.